1. Field of the Invention
The invention relates generally to long time-constant integrating circuits providing an adjustable integration period utilizing capacitors of a size suitable for incorporation in an integrated circuit, with the integrating circuit being capable of performing over a wide linear dynamic range with gain.
2. Description of the Prior Art
A particularly useful circuit required in many communication applications is the integrating circuit which performs the mathematical operation of integration. There are many conventional integrating circuits, three of which are illustrated in FIGS. 1A, 1B and 1C. These circuits have been successfully used commercially. However, each of these only approximates the integration operation over a limited period of time.
Further, these circuits cannot adjust the total integration time without using additional hardware such as resistors, capacitors, switches and control circuitry. In addition to the cost increase due to this additional hardware, adjustable circuits fashioned in such a manner will exceed most communication specifications which require compact, lightweight circuitry.
As shown in FIG. 1A, a basic integrating circuit consists of a resistor R and a capacitor C and provides a limited version of the operation of mathematical integration. This is demonstrated by examining the output of the circuit in FIG. 1A, in response to an input such as a voltage step input. The following formula gives the value of the output voltage V.sub.out as a function of the time t, where t is the time base in seconds after the rising edge of the input step is applied, and as a function of the amplitude A of the step voltage applied as the input V.sub.in. EQU V.sub.OUT (t)=A(.vertline.-e.sup.-t/RC)t.sub.o&gt; t&gt;0 (1).
FIG. 2 graphically shows the response of the circuit in FIG. 1A. The step voltage applied as V.sub.in is represented by curve 30. Curve 31 represents V.sub.out (t) in circuit 1A and approximates the output of an ideal integrator, curve 32, when t is close to zero. Capacitor C must have a breakdown voltage greater than V.sub.in to prevent a discharge. Alternatively, the period of integration must be less than the time capacitor C requires to reach a fully charged condition. Curve 33, which is a graphical representation of the following formula, shows that the circuit 1A requires time to discharge: EQU V.sub.OUT (t)=Ae.sup.-(t-to)/RC t&gt;t.sub.o ( 2).
Therefore, the prior art circuit of FIG. 1A has limited applicability due to the limitations on capacitor size and integration period. Furthermore, during the discharge time represented by Curve 33, the circuit is useless for performing the integration function.
While the prior art integration circuit in FIG. 1B provides a closer approximation of an ideal integrator, this circuit is also limited. Long time-constants for this circuit require proportionately large capacitors and resistors. This is a particular problem with integrated circuits in that the maximum size capacitor capable of being fabricated internally on a chip is of the order of tens of picofarads. Similarly, the maximum resistor size on an IC is a few kiloohms. Capacitors of that size yield time-constants which are insufficient in length for most communication applications. Also, the useful output of the circuit is inversely proportional to the size of the capacitors and resistors.
The circuit of FIG. 1B also suffers, as the circuit of FIG. 1A, from requiring time to discharge in which the integration function cannot be performed. In order to decrease this discharge time, most integration circuits shunt a low resistance across the capacitor. It is not practical to reduce this resistor below a value of tens of ohms, which still requires some recovery time.
One prior art solution is the use of at least two integrating circuits, so that one is operational while the other circuit is discharging. As this shunt resistance increases in value, for example, approximating the resistance R, in FIG. 1A or 1B, the required number of parallel integrating circuits likewise increases as shown by the following formula: EQU 69 R'/R+1=.eta. R'=SHUNT RESISTANCE (3).
In this formula, .eta., when rounded to the next larger integer, gives the number of integrating circuits for an application requiring a 60 db linear dynamic range. Parallel integrating circuits require additional hardware for switching, control and discharge. This makes the circuits in FIGS. 1A and 1B impractical to incorporate into integrated circuits except in extremely limited applications.
The circuit in FIG. 1C illustrates a common base transistor circuit which functions as an integrator and provides a very close approximation of the ideal integrator. The bipolar junction transistor EBC shown in the circuit of FIG. 1C is redrawn to the equivalent circuit using hybrid parameters and is shown in FIG. 3. The emitter current is represented by i.sub.e. The collector current is shown as i.sub.c. The parameter h.sub.ie is equal to the short circuit input impedance. The parameter h.sub.oe is equal to the open circuit output admittance. As 1/h.sub.oe approaches infinity, the circuit is representable as a current source feeding a capacitor, as described by the following formula, which is the mathematical representation of an ideal integrator: EQU V.sub.OUT (t)=.vertline./Ci.sub.c (t)dt (4)
The circuit in FIG. 1C is still vulnerable to the same problems of the circuits in FIGS. 1A and 1B such as saturating and, thus, producing non-linearities. The circuit in FIG. 1C must also be discharged before being usable again. The time-constant of the common base integrator in FIG. 1C is still directly proportional to the size of the capacitor C and, thus, is quite limited to those applications requiring only short time-constants if the required capacitor is to be included in the integrated circuit. Finally, the circuit in FIG. 1C cannot achieve variable integration time without using additional resistors, capacitors, switches and controls.